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<source lang="diff">--- vl.h Wed May 9 20:25:36 2007 +++ vl.h Thu May 17 09:04:44 2007 @@ -1011,6 +1011,7 @@

int DMA_write_memory (int nchan, void *buf, int pos, int size);
void DMA_hold_DREQ (int nchan);
void DMA_release_DREQ (int nchan);

+void DMA_set_TC (int nchan);

void DMA_schedule(int nchan);
void DMA_run (void);
void DMA_init (int high_page_enable);

--- hw/dma.c Mon Nov 21 23:29:56 2005 +++ hw/dma.c Wed May 16 13:02:30 2007 @@ -311,6 +311,16 @@

    dma_controllers[ncont].status |= 1 << (ichan + 4);
}

+void DMA_set_TC (int nchan) +{ + int ncont, ichan; + + ncont = nchan > 3; + ichan = nchan & 3; + linfo ("tc set cont=%d chan=%d\n", ncont, ichan); + dma_controllers[ncont].status |= 1 << ichan; +} +

void DMA_release_DREQ (int nchan)
{
    int ncont, ichan;

--- hw/fdc.c Sat Apr 14 13:01:32 2007 +++ hw/fdc.c Wed May 16 17:14:54 2007 @@ -917,7 +920,10 @@

    fdctrl->fifo[6] = FD_SECTOR_SC;
    fdctrl->data_dir = FD_DIR_READ;
    if (fdctrl->state & FD_CTRL_BUSY) {

- DMA_release_DREQ(fdctrl->dma_chann); + if (fdctrl->dma_en) { + DMA_release_DREQ(fdctrl->dma_chann); + DMA_set_TC(fdctrl->dma_chann); + }

        fdctrl->state &= ~FD_CTRL_BUSY;
    }
    fdctrl_set_fifo(fdctrl, 7, 1);

</source>

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